Title: "Low Power CMOS Based Dual Mode Logic Gates "
         

Page(s): 32 - 38
Authors: S Sujeetha,Dr. V Renganathan

Abstract

The advancement in technology and the expansion of mobile applications, power consumption has become a primary focus of attention in Very Large Scale Integration (VLSI) digital design. Recently digital sub-threshold circuit design has become a very promising method for ultra-low power applications. Circuits operating in the sub-threshold region utilize a supply voltage that comes close to or even less than the threshold voltages of the transistors, so it allows significant reduction of both dynamic and static power. A Dual Mode Logic (DML) gate, for selectable operation in either of static and dynamic modes. By scaling down the area there should be a need arise to scale down the supply voltage as well as threshold voltages of the device. It can cause static power dissipation to dominate dynamic power dissipation. To reduce the power consumption and dissipation of the circuit and increase the life time of the battery normally used in mobile phones and personal digital assistants Power Gated Sleep method can be applied. During sleep to active mode transition the stacked sleep transistors connected below the pull-down network are ON after a small duration. During the instant circuit should be experiences the Ground Bounce Noise (GBN). Inserting proper amount of delay which is less than the discharge time of the sleep transistor GBN will be reduced. The output of the circuit should be high enough to drive the another circuit. The simulations were done in TannerEDA 13.0 tool and power consumption of the proposed DML gates compared with Sleep and Dual Sleep methods in the 250-nm process.

Index Terms—Dual Mode Logic gates, Ground Bounce Noise, Sub-Threshold Region.