Title: "Implementation of Low Power Dynamic Logic CMOS Circuits "
         

Page(s): 21 - 26
Authors: J Mercy, Priya Stalin

Abstract

Today in Very Large Scale Integration (VLSI) technology several applications require high speed operation. To achieve this dual output dynamic logic using Source Coupled Logic (SCL) topology was designed and it provides high speed operation with area and power over head. In order to reduce the power in dual output dynamic logic with optimizable speed of operation half swing is introduced. With the help of half swing without altering the operation of the logic function power is reduced. The half swing technique is applied to clock as well as input level. The existing system NMOS (N- type Metal Oxide Semiconductor) differential tree logic is applied to NAND, NOR, Exclusive -NOR (EX-NOR), half adder, and full adder. Due to the usage of NMOS differential tree logic this circuit gives true and complementary outputs. The power dissipation of NMOS differential tree logic is 80% greater than Complementary Metal Oxide Semiconductor (CMOS). Compared to the existing system the power dissipation is reduced by 46% in the proposed half swing. The delay achieved with existing system is 0.2 ns. The delay in the proposed system increases by 33% which is less compared to power dissipation reduction that is achieved. Advantages of dual output dynamic logic circuit is it increases the speed, avoids noise, no charge sharing problem, no short circuit power dissipation and it eliminates monotonicity problem.

Dual output dynamic logic, SCL, NMOS differential tree, Half swing